Microelectronic devices are used in cell phones, pagers, personal digital assistants, computers, and many other products. A die-level packaged microelectronic device can include a microelectronic die, an interposer substrate or lead frame attached to the die, and a molded casing around the die. The microelectronic die generally has an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are coupled to terminals on the interposer substrate or lead frame. The interposer substrate can also include ball-pads coupled to the terminals by conductive traces in a dielectric material. An array of solder balls is configured so that each solder ball contacts a corresponding ball-pad to define a “ball-grid” array. Packaged microelectronic devices with ball-grid arrays are generally higher grade packages that have lower profiles and higher pin counts than conventional chip packages that use a lead frame.
Die-level packaged microelectronic devices are typically made by (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to singulate the dies, (c) attaching individual dies to an individual interposer substrate, (d) wire-bonding the bond-pads to the terminals of the interposer substrate, and (e) encapsulating the dies with a molding compound. Mounting individual dies to individual interposer substrates is time consuming and expensive. Also, as the demand for higher pin counts and smaller packages increases, it becomes more difficult to (a) form robust wire-bonds that can withstand the forces involved in molding processes and (b) accurately form other components of die-level packaged devices. Therefore, packaging processes have become a significant factor in producing semiconductor and other microelectronic devices.
Another process for packaging microelectronic devices is wafer-level packaging. In wafer-level packaging, a plurality of microelectronic dies are formed on a wafer and a redistribution layer is formed over the dies. The redistribution layer includes a dielectric layer, a plurality of ball-pad arrays on the dielectric layer, and a plurality of traces coupled to individual ball-pads of the ball-pad arrays. Each ball-pad array is arranged over a corresponding microelectronic die, and the traces couple the ball-pads in each array to corresponding bond-pads on the die. After forming the redistribution layer on the wafer, a stenciling machine deposits discrete blocks of solder paste onto the ball-pads of the redistribution layer. The solder paste is then reflowed to form solder balls or solder bumps on the ball-pads. After forming the solder balls on the ball-pads, the wafer is cut to singulate the dies. Microelectronic devices packaged at the wafer level can have high pin counts in a small area, but they are not as robust as devices packaged at the die level.
In the process of forming and packaging microelectronic devices, numerous holes are formed in the wafer and subsequently filled with material to form conductive lines, bond-pads, interconnects, and other features. One existing method for forming holes in wafers is reactive ion etching (RIE). In RIE, many holes on the wafer can be formed simultaneously. RIE, however, has several drawbacks. For example, RIE may attack features in the wafer that should not be etched, and the RIE process is slow. Typically, RIE processes have removal rates of from approximately 5 μ/min to approximately 50 μ/min. Moreover, RIE requires several additional process steps, such as masking and cleaning.
Another existing method for forming holes in wafers is laser ablation. A conventional laser ablation process includes forming a series of test holes in a test wafer to determine the time required to form various through holes in the test wafer. The test holes are formed by directing the laser beam to selected points on the wafer for different periods of time. The test wafer is subsequently inspected manually to determine the time required to form a through hole in the wafer. The actual time for use in a run of identical wafers is then calculated by adding an overdrill factor to the time required to drill the test holes to ensure that the holes extend through the wafer. A run of identical wafers is then processed based on the data from the test wafer. A typical laser can form more than 10,600 holes through a 750 Å wafer in less than two minutes.
Laser ablation, however, has several drawbacks. For example, the heat from the laser beam creates a heat-affected zone in the wafer in which doped elements can migrate. Moreover, because the wafer thickness is generally non-uniform, the laser may not form a through hole in thick regions of the wafer or the wafer may be overexposed to the laser beam and consequently have a large heat-affected zone in thin regions of the wafer. Accordingly, there exists a need to improve the process of forming through holes or deep blind holes in microfeature workpieces.